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semiconductor technical data 31 rev 6 ? motorola, inc. 1995 10/95
! " highperformance silicongate cmos the mc54/74hc646 is identical in pinout to the ls646. the device inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with lsttl outputs. these devices are bus transceivers with d flipflops. depending on the status of the datasource selection pins, data may be routed to the outputs either f ro m t h e f lipflop s o r t ransmitte d r ealtim e f ro m t h e i nputs ( see function table and application information). the o utpu t e nabl e a n d t h e d irectio n p in s c ontro l t h e t ransceiver's function. b u s a a n d b u s b c annot b e r oute d a s o utput s t o e ac h o ther simultaneously, but can be routed as inputs to the a and b flipflops. also, the a a n d b f lipflop s c a n b e r oute d a s o utput s t o b u s a a n d b u s b . additionally , when either or both of the ports are in the highimpedance state, t hes e i / o p in s m a y b e u se d a s i nput s t o t h e d f lipflop s f o r d ata storage. the u se r s houl d n ot e t ha t b ecaus e t h e c lock s a r e n o t g ate d w it h t he direction and output enable pins, data at the a and b ports may be clocked into the storage flipflops at any time. ? output drive capability: 15 lsttl loads ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 2 to 6 v ? low input current: 1 m a ? high noise immunity characteristic of cmos devices ? in compliance with the requirements defined by jedec standard no. 7a ? chip complexity: 780 fets or 195 equivalent gates logic diagram a data port b data port a0 a1 a2 a3 a4 a5 a6 a7 11 10 9 8 7 6 5 4 20 b0 19 18 17 16 15 14 13 b1 b2 b3 b4 b5 b6 b7 21 3 1 23 2 22 atob source btoa source btoa clock atob clock direction output enable flipflop clocks data source selection inputs pin 24 = v cc pin 12 = gnd pin assignment a2 a0 direction atob source atob clock a4 a3 a1 b0 output enable btoa source btoa clock v cc b5 b4 b3 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 13 11 12 21 22 23 24 b7 b6 b2 b1 a7 gnd a6 a5 n suffix plastic package case 72403 ordering information mc54hcxxxj mc74hcxxxn mc74hcxxxdw ceramic plastic soic 1 24 j suffix ceramic package case 75802 dw suffix soic package case 751e04 1 24 1 24
mc54/74hc646 motorola highspeed cmos logic data dl129 e rev 6 32 ??????????????????????? ??????????????????????? ??????????????????????? ??????????????????????? maximum ratings* ??? ??? ??? ??? symbol ?????????????? ?????????????? ?????????????? ?????????????? parameter ?????? ?????? ?????? ?????? value ??? ??? ??? ??? unit ??? ??? ??? ??? v cc ?????????????? ?????????????? ?????????????? ?????????????? dc supply voltage (referenced to gnd) ?????? ?????? ?????? ?????? 0.5 to + 7.0 ??? ??? ??? ??? v ??? ??? ??? ??? v in ?????????????? ?????????????? ?????????????? ?????????????? dc input voltage (referenced to gnd) ?????? ?????? ?????? ?????? 1.5 to v cc + 1.5 ??? ??? ??? ??? v ??? ??? ??? ??? v i/o ?????????????? ?????????????? ?????????????? ?????????????? dc i/o voltage (referenced to gnd) ?????? ?????? ?????? ?????? 0.5 to v cc + 0.5 ??? ??? ??? ??? v ??? ??? ??? ??? i in ?????????????? ?????????????? ?????????????? ?????????????? dc input current, per pin ?????? ?????? ?????? ?????? 20 ??? ??? ??? ??? ma ??? ??? ??? ??? i i/o ?????????????? ?????????????? ?????????????? ?????????????? dc i/o current, per pin ?????? ?????? ?????? ?????? 35 ??? ??? ??? ??? ma ??? ??? ??? ??? i cc ?????????????? ?????????????? ?????????????? ?????????????? dc supply current, v cc and gnd pins ?????? ?????? ?????? ?????? 75 ??? ??? ??? ??? ma ??? ??? ??? ??? p d ?????????????? ?????????????? ?????????????? ?????????????? power dissipation in still air, plastic or ceramic dip2 soic package2 ?????? ?????? ?????? ?????? 750 500 ??? ??? ??? ??? mw ??? ??? ??? ??? t stg ?????????????? ?????????????? ?????????????? ?????????????? storage temperature ?????? ?????? ?????? ?????? 65 to + 150 ??? ??? ??? ??? c ??? ??? ??? ??? ??? t l ?????????????? ?????????????? ?????????????? ?????????????? ?????????????? lead t emperature, 1 mm from case for 10 seconds (plastic dip or soic package) (ceramic dip) ?????? ?????? ?????? ?????? ?????? 260 300 ??? ??? ??? ??? ??? c * maximum ratings are those values beyond which damage to the device may occur . functional operation should be restricted to the recommended operating conditions. 2derating e plastic dip: 10 mw/ c from 65 to 125 c ceramic dip: 10 mw/ c from 100 to 125 c soic package: 7 mw/ c from 65 to 125 c for high frequency or heavy load considerations, see chapter 2 of the motorola highspeed cmos data book (dl129/d). recommended operating conditions ???? ???? ???? ???? symbol ?????????????? ?????????????? ?????????????? ?????????????? parameter ??? ??? ??? ??? min ??? ??? ??? ??? max ??? ??? ??? ??? unit ???? ???? ???? ???? v cc ?????????????? ?????????????? ?????????????? ?????????????? dc supply voltage (referenced to gnd) ??? ??? ??? ??? 2.0 ??? ??? ??? ??? 6.0 ??? ??? ??? ??? v ???? ???? ???? ???? v in , v out ?????????????? ?????????????? ?????????????? ?????????????? dc input voltage, output voltage (referenced to gnd) ??? ??? ??? ??? 0 ??? ??? ??? ??? v cc ??? ??? ??? ??? v ???? ???? ???? ???? t a ?????????????? ?????????????? ?????????????? ?????????????? operating temperature, all package types ??? ??? ??? ??? 55 ??? ??? ??? ??? + 125 ??? ??? ??? ??? c ???? ???? ???? ???? ???? t r , t f ?????????????? ?????????????? ?????????????? ?????????????? ?????????????? input rise and fall time v cc = 2.0 v (figure 1) v cc = 4.5 v v cc = 6.0 v ??? ??? ??? ??? ??? 0 0 0 ??? ??? ??? ??? ??? 1000 500 400 ??? ??? ??? ??? ??? ns dc electrical characteristics (voltages referenced to gnd) ???? ???? ???? ???? symbol ????????? ????????? ????????? ????????? parameter ????????? ????????? ????????? ????????? test conditions ???? ???? ???? ???? v cc v ????????? ????????? ????????? ????????? guaranteed limit ??? ??? ??? ??? unit ???? ???? ???? ???? symbol ????????? ????????? ????????? ????????? parameter ????????? ????????? ????????? ????????? test conditions ???? ???? ???? ???? v cc v ??? ??? ??? ??? 55 to 25 c ???? ???? ???? ???? 85 c ???? ???? ???? ???? 125 c ??? ??? ??? ??? unit ???? ???? ???? ???? ???? ???? v ih ????????? ????????? ????????? ????????? ????????? ????????? minimum highlevel input voltage ????????? ????????? ????????? ????????? ????????? ????????? v out = 0.1 v or v cc 0.1 v |i out | 20 m a ???? ???? ???? ???? ???? ???? 2.0 4.5 6.0 ??? ??? ??? ??? ??? ??? 1.5 3.15 4.2 ???? ???? ???? ???? ???? ???? 1.5 3.15 4.2 ???? ???? ???? ???? ???? ???? 1.5 3.15 4.2 ??? ??? ??? ??? ??? ??? v ???? ???? ???? ???? ???? v il ????????? ????????? ????????? ????????? ????????? maximum lowlevel input voltage ????????? ????????? ????????? ????????? ????????? v out = 0.1 v or v cc 0.1 v |i out | 20 m a ???? ???? ???? ???? ???? 2.0 4.5 6.0 ??? ??? ??? ??? ??? 0.3 0.9 1.2 ???? ???? ???? ???? ???? 0.3 0.9 1.2 ???? ???? ???? ???? ???? 0.3 0.9 1.2 ??? ??? ??? ??? ??? v ???? ???? ???? ???? ???? v oh ????????? ????????? ????????? ????????? ????????? minimum highlevel output voltage ????????? ????????? ????????? ????????? ????????? v in = v ih or v il |i out | 20 m a ???? ???? ???? ???? ???? 2.0 4.5 6.0 ??? ??? ??? ??? ??? 1.9 4.4 5.9 ???? ???? ???? ???? ???? 1.9 4.4 5.9 ???? ???? ???? ???? ???? 1.9 4.4 5.9 ??? ??? ??? ??? ??? v ???? ???? ???? ???? ???? ????????? ????????? ????????? ????????? ????????? ????????? ????????? ????????? ????????? ????????? v in = v ih or v il |i out | 6.0 ma |i out | 7.8 ma ???? ???? ???? ???? ???? 4.5 6.0 ??? ??? ??? ??? ??? 3.98 5.48 ???? ???? ???? ???? ???? 3.84 5.34 ???? ???? ???? ???? ???? 3.70 5.20 ??? ??? ??? ??? ??? ???? ???? ???? ???? ???? v ol ????????? ????????? ????????? ????????? ????????? maximum lowlevel output voltage ????????? ????????? ????????? ????????? ????????? v in = v ih or v il |i out | 20 m a ???? ???? ???? ???? ???? 2.0 4.5 6.0 ??? ??? ??? ??? ??? 0.1 0.1 0.1 ???? ???? ???? ???? ???? 0.1 0.1 0.1 ???? ???? ???? ???? ???? 0.1 0.1 0.1 ??? ??? ??? ??? ??? v ???? ???? ???? ???? ????????? ????????? ????????? ????????? ????????? ????????? ????????? ????????? v in = v ih or v il |i out | 6.0 ma |i out | 7.8 ma ???? ???? ???? ???? 4.5 6.0 ??? ??? ??? ??? 0.26 0.26 ???? ???? ???? ???? 0.33 0.33 ???? ???? ???? ???? 0.40 0.40 ??? ??? ??? ??? ???? ???? ???? ???? ???? i in ????????? ????????? ????????? ????????? ????????? maximum input leakage current ????????? ????????? ????????? ????????? ????????? v in = v cc or gnd (pins 1, 2, 3, 21, 22, and 23) ???? ???? ???? ???? ???? 6.0 ??? ??? ??? ??? ??? 0.1 ???? ???? ???? ???? ???? 1.0 ???? ???? ???? ???? ???? 1.0 ??? ??? ??? ??? ??? m a this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however , precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance cir - cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open. i/o pins must be connected to a properly terminated line or bus.
mc54/74hc646 highspeed cmos logic data dl129 e rev 6 33 motorola dc electrical characteristics (voltages referenced to gnd) ??? ??? ??? ??? ??? unit ???? ???? ???? ???? ???? 125 c ???? ???? ???? ???? ???? 85 c ??? ??? ??? ??? ??? 55 to 25 c ???? ???? ???? ???? ???? v cc v ????????? ????????? ????????? ????????? ????????? test conditions ????????? ????????? ????????? ????????? ????????? parameter ???? ???? ???? ???? ???? symbol ???? ???? ???? ???? ???? i oz ????????? ????????? ????????? ????????? ????????? maximum threestate leakage current ????????? ????????? ????????? ????????? ????????? output in highimpedance state v in = v il or v ih v out = v cc or gnd, i/o pins ???? ???? ???? ???? ???? 6.0 ??? ??? ??? ??? ??? 0.5 ???? ???? ???? ???? ???? 5.0 ???? ???? ???? ???? ???? 10 ??? ??? ??? ??? ??? m a ???? ???? ???? ???? i cc ????????? ????????? ????????? ????????? maximum quiescent supply current (per package) ????????? ????????? ????????? ????????? v in = v cc or gnd i out = 0 m a ???? ???? ???? ???? 6.0 ??? ??? ??? ??? 8 ???? ???? ???? ???? 80 ???? ???? ???? ???? 160 ??? ??? ??? ??? m a note: information on typical parametric values can be found in chapter 2 of the motorola highspeed cmos data book (dl129/d).
mc54/74hc646 motorola highspeed cmos logic data dl129 e rev 6 34 ac electrical characteristics (c l = 50 pf, input t r = t f = 6 ns) ???? ???? ???? ???? symbol ????????????????? ????????????????? ????????????????? ????????????????? parameter ???? ???? ???? ???? v cc v ????????? ????????? ????????? ????????? guaranteed limit ??? ??? ??? ??? unit ???? ???? ???? ???? ???? symbol ????????????????? ????????????????? ????????????????? ????????????????? ????????????????? parameter ???? ???? ???? ???? ???? v cc v ??? ??? ??? ??? ??? 55 to 25 c ???? ???? ???? ???? ???? 85 c ???? ???? ???? ???? ???? 125 c ??? ??? ??? ??? ??? unit ???? ???? ???? ???? ???? f max ????????????????? ????????????????? ????????????????? ????????????????? ????????????????? maximum clock frequency (50% duty cycle) (figures 3, 4 and 9) ???? ???? ???? ???? ???? 2.0 4.5 6.0 ??? ??? ??? ??? ??? 6.0 30 35 ???? ???? ???? ???? ???? 4.8 24 28 ???? ???? ???? ???? ???? 4.0 20 24 ??? ??? ??? ??? ??? mhz ???? ???? ???? ???? ???? t plh , t phl ????????????????? ????????????????? ????????????????? ????????????????? ????????????????? maximum propagation delay, input a to output b (or input b to output a) (figures 1, 2 and 9) ???? ???? ???? ???? ???? 2.0 4.5 6.0 ??? ??? ??? ??? ??? 170 34 29 ???? ???? ???? ???? ???? 215 43 37 ???? ???? ???? ???? ???? 255 51 43 ??? ??? ??? ??? ??? ns ???? ???? ???? ???? ???? ???? t plh , t phl ????????????????? ????????????????? ????????????????? ????????????????? ????????????????? ????????????????? maximum propagation delay, atob clock to output b (or btoa clock to output a) (figures 3, 4 and 9) ???? ???? ???? ???? ???? ???? 2.0 4.5 6.0 ??? ??? ??? ??? ??? ??? 220 44 37 ???? ???? ???? ???? ???? ???? 275 55 47 ???? ???? ???? ???? ???? ???? 330 66 56 ??? ??? ??? ??? ??? ??? ns ???? ???? ???? ???? ???? t plh , t phl ????????????????? ????????????????? ????????????????? ????????????????? ????????????????? maximum propagation delay, atob source to output b (or btoa source to output a) (figures 5, 6 and 9) ???? ???? ???? ???? ???? 2.0 4.5 6.0 ??? ??? ??? ??? ??? 170 34 29 ???? ???? ???? ???? ???? 215 43 37 ???? ???? ???? ???? ???? 255 51 43 ??? ??? ??? ??? ??? ns ???? ???? ???? ???? ???? t plz , t phz ????????????????? ????????????????? ????????????????? ????????????????? ????????????????? maximum propagation delay, output enable to output a or b (figures 7, 8 and 10) ???? ???? ???? ???? ???? 2.0 4.5 6.0 ??? ??? ??? ??? ??? 175 35 30 ???? ???? ???? ???? ???? 220 44 37 ???? ???? ???? ???? ???? 265 53 45 ??? ??? ??? ??? ??? ns ???? ???? ???? ???? ???? ???? t pzl , t pzh ????????????????? ????????????????? ????????????????? ????????????????? ????????????????? ????????????????? maximum propagation delay, direction or output enable to output a or b (figures 7, 8 and 10) ???? ???? ???? ???? ???? ???? 2.0 4.5 6.0 ??? ??? ??? ??? ??? ??? 175 35 30 ???? ???? ???? ???? ???? ???? 220 44 37 ???? ???? ???? ???? ???? ???? 265 53 45 ??? ??? ??? ??? ??? ??? ns ???? ???? ???? ???? ???? t tlh , t thl ????????????????? ????????????????? ????????????????? ????????????????? ????????????????? maximum output transition time, any output (figures 1 and 9) ???? ???? ???? ???? ???? 2.0 4.5 6.0 ??? ??? ??? ??? ??? 60 12 10 ???? ???? ???? ???? ???? 75 15 13 ???? ???? ???? ???? ???? 90 18 15 ??? ??? ??? ??? ??? ns ???? ???? ???? ???? c in ????????????????? ????????????????? ????????????????? ????????????????? maximum input capacitance ???? ???? ???? ???? e ??? ??? ??? ??? 10 ???? ???? ???? ???? 10 ???? ???? ???? ???? 10 ??? ??? ??? ??? pf ???? ???? ???? ???? ???? c out ????????????????? ????????????????? ????????????????? ????????????????? ????????????????? maximum threestate output capacitance (output in highimpedance state) ???? ???? ???? ???? ???? e ??? ??? ??? ??? ??? 15 ???? ???? ???? ???? ???? 15 ???? ???? ???? ???? ???? 15 ??? ??? ??? ??? ??? pf notes: 1. for propagation delays with loads other than 50 pf , see chapter 2 of the motorola highspeed cmos data book (dl129/d). 2. information on typical parametric values can be found in c hapter 2 of the motorola highspeed cmos data book (dl129/d). c pd power dissipation capacitance (per channel)* typical @ 25 c, v cc = 5.0 v pf c pd power dissipation capacitance (per channel)* 60 pf * used to determine the noload dynamic power consumption: p d = c pd v cc 2 f + i cc v cc . for load considerations, see chapter 2 of the motorola highspeed cmos data book (dl129/d). timing requirements (input t r = t f = 6 ns) ???? ???? ???? ???? symbol ????????????????? ????????????????? ????????????????? ????????????????? parameter ???? ???? ???? ???? v cc v ????????? ????????? ????????? ????????? guaranteed limit ??? ??? ??? ??? unit ???? ???? ???? ???? ???? symbol ????????????????? ????????????????? ????????????????? ????????????????? ????????????????? parameter ???? ???? ???? ???? ???? v cc v ??? ??? ??? ??? ??? 55 to 25 c ???? ???? ???? ???? ???? 85 c ???? ???? ???? ???? ???? 125 c ??? ??? ??? ??? ??? unit ???? ???? ???? ???? ???? t su ????????????????? ????????????????? ????????????????? ????????????????? ????????????????? minimum setup time, input a to atob clock (or input b to btoa clock) (figures 3 and 4) ???? ???? ???? ???? ???? 2.0 4.5 6.0 ??? ??? ??? ??? ??? 100 20 17 ???? ???? ???? ???? ???? 125 25 21 ???? ???? ???? ???? ???? 150 30 26 ??? ??? ??? ??? ??? ns ???? ???? ???? ???? ???? ???? t h ????????????????? ????????????????? ????????????????? ????????????????? ????????????????? ????????????????? minimum hold time, atob clock to input a (or btoa clock to input b) (figures 3 and 4) ???? ???? ???? ???? ???? ???? 2.0 4.5 6.0 ??? ??? ??? ??? ??? ??? 5 5 5 ???? ???? ???? ???? ???? ???? 5 5 5 ???? ???? ???? ???? ???? ???? 5 5 5 ??? ??? ??? ??? ??? ??? ns ???? ???? ???? ???? ???? t w ????????????????? ????????????????? ????????????????? ????????????????? ????????????????? minimum pulse width, atob clock (or btoa clock) (figures 3 and 4) ???? ???? ???? ???? ???? 2.0 4.5 6.0 ??? ??? ??? ??? ??? 80 16 14 ???? ???? ???? ???? ???? 100 20 17 ???? ???? ???? ???? ???? 120 24 20 ??? ??? ??? ??? ??? ns ???? ???? ???? ???? ???? t r , t f ????????????????? ????????????????? ????????????????? ????????????????? ????????????????? maximum input rise and fall times (figure 1) ???? ???? ???? ???? ???? 2.0 4.5 6.0 ??? ??? ??? ??? ??? 1000 500 400 ???? ???? ???? ???? ???? 1000 500 400 ???? ???? ???? ???? ???? 1000 500 400 ??? ??? ??? ??? ??? ns note: information on typical parametric values can be found in chapter 2 of the motorola highspeed cmos data book (dl129/d).
mc54/74hc646 highspeed cmos logic data dl129 e rev 6 35 motorola function table e hc646 control inputs data port status storage flip flop states description of operation output enable direc tion atob clock btoa clock atob source btoa source a b q a q b description of operation h x h, l, h, l, x x input: x input: x no change no change the output functions of the a and b ports are disabled x x l h x x x x l h l h x x x x l h the ports may be used as inputs to the storage flipflops. data at the in- puts are clocked into the flipflops with the rising edge of the clocks. l h input: output: the output mode of the b data port is enabled and behaves according to the following logic equation: b = [a ? (atob source )] + [q a ? (atob source)] h, l, x* l x l h l h no change no change no change no change 1.) when atob source is low , the data at the a data port are dis - played at the b data port. the states of the storage flipflops are not affected. h x x q a no change no change 2.) when atob source is high, the states of the a storage flipflops are displayed at the b data port. x* l x l h l h l h no change no change 3.) when atob source is low , the data at the a data port are clocked into the a storage flipflops by a ris - ingedge signal on the atob clock. h x l h q a q a l h no change no change 4.) when atob source is high, the data at the a data port are clocked into the a storage flipflops by a ris - ingedge signal on the atob clock. the states, q a , of the stor- age flipflops propagate directly to the b data port. l l output: input: the output mode of the a data port is enabled and behaves according to the following logic equation: a = [b ? (btoa source )] + [q b ? (btoa source)] x* h, l, x l l h l h no change no change no change no change 1.) when btoa source is low , the data at the b data port are dis - played at the a data port. the states of the storage flipflops are not affected. x h q b x no change no change 2.) when btoa source is high, the states of the b storage flipflops are displayed at the a data port. x* x l l h l h no change no change l h 3.) when btoa source is low , the data at the b data port are clocked into the b storage flipflops by a ris - ingedge signal on the btoa clock. x h q b q b l h no change no change l h 4.) when btoa source is high, the data at the b data port are clocked into the b storage flipflops by a ris - ingedge signal on the btoa clock. the states, q b , of the stor- age flipflops propagate directly to the a data port. * the clocks are not internally gated with either the output enables or the source inputs. therefore, data at the a and b ports may be clocked into the storage flipflops at any time.
mc54/74hc646 motorola highspeed cmos logic data dl129 e rev 6 36 bus a a flip flops b flip flops control logic control logic (3) (21) (1) (23) (2) (22) direction output enable atob clock btoa clock atob source btoa source x h x x control pins (3) (21) (1) (23) (2) (22) direction output enable atob clock btoa clock atob source btoa source h l l x control pins data storage from a and/or b bus realtime transfer from bus a to bus b control logic x x typical applications (3) (21) (1) (23) (2) (22) direction output enable atob clock btoa clock atob source btoa source l l x l control pins realtime transfer from bus b to bus a x x bus b bus a bus b a flip flops b flip flops bus a a flip flops b flip flops bus b
mc54/74hc646 highspeed cmos logic data dl129 e rev 6 37 motorola timing diagrams and switching diagrams e hc646 90% figure 1. a data port = input, b data port = output t r t f v cc gnd figure 2. a data port = output, b data port = input note: = don't care state output enable direction atob source btoa source a data port b data port output enable direction btoa source atob source b data port a data port v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd 50% 10% 10% 50% 90% t tlh t thl t plh t phl 90% 50% 10% 50% t r t f t plh t phl
mc54/74hc646 motorola highspeed cmos logic data dl129 e rev 6 38 figure 3. a data port = input, b data port = output figure 4. b data port = input, a data port = output output enable direction btoa source atob source btoa clock b data port output enable direction btoa source atob source b data port a data port a data port atob clock btoa clock atob clock v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd 50% 50% 50% 50% 50% 50% t h t h t w t w 1/f max 1/f max t phl t plh t phl t plh t su t su
mc54/74hc646 highspeed cmos logic data dl129 e rev 6 39 motorola b data port a data port output enable direction internal q a (flipflop a) internal q b (flipflop b) btoa source atob source v cc gnd notes: 1. b data port (output) changes from the level of the storage flipflop, q a , to the level of a data port (input). 2. b data port (output) changes from the level of the a data port (input) to the level of the storage flipflop, q a. 3. the a storage flipflop, atob source, and a data port (input) have simultaneously changed states. figure 5. a data port = input, b data port = output 1 2 3 v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd 50% t plh t phl 50% t plh t phl
mc54/74hc646 motorola highspeed cmos logic data dl129 e rev 6 310 notes: 1. a data port (output) changes from the level of the storage flipflop, q b , to the level of b data port (input). 2. a data port (output) changes from the level of the b data port (input) to the level of the storage flipflop, q b. 3. the b storage flipflop, btoa source, and b data port (input) have simultaneously changed states for the purpose of this 3. example. a data port (output) is now displaying the voltage level of b data port (input). figure 6. a data port = output, b data port = input 1 2 3 b data port a data port output enable direction internal q a (flipflop a) internal q b (flipflop b) btoa source atob source v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd 50% t plh t phl t plh t phl 50% pin descriptions inputs/outputs a0 a7 (pins 4 11) and b0 b7 (pins 20 13) a and b data ports. these pins may function either as in - puts to or outputs from the transceivers. control inputs output enable (pin 21) activelow output enable. when this pin is low , the outputs are enabled and function normally . when this pin is high, the a and b data ports are in highimpedance states. see the function table. direction (pin 3) data direction control. when the output enable pin is low, this control pin determines the direction of data flow . when direction is high, the a data ports are inputs and the b data ports are outputs. when direction is low , the a data ports are outputs and the b data ports are inputs. atob clock, btoa clock (pins 1, 23) clocks f or t h e i nterna l d f lipflops . w it h a l owtohigh transition on the appropriate clock pin, data on the a (or b) inputs are clocked into the internal a (or b) flipflops. these clocks are not internally gated with the output enable or the direction pins, therefore data at the a and b pins may be clocked into the storage flipflops at any time. atob source, btoa source (pins 2, 22) datasource selection pins. depending upon the states of these pins (see the function table), data at the outputs may come either from the inputs or from the d flipflops.
mc54/74hc646 highspeed cmos logic data dl129 e rev 6 311 motorola v cc gnd high impedance output enable direction data port a data port a data port b data port b data port a = input data port b = output data port a = output data port b = input * includes all probe and jig capacitance c l * test point device under test output * includes all probe and jig capacitance c l * test point device under test output connect to v cc when testing t plz and t pzl . connect to gnd when testing t phz and t pzh . 1 k w output enable output a or b output a or b 50% 50% 50% 90% 10% t pzl t plz t pzh t phz v cc gnd high impedance v ol v oh high impedance v cc gnd v oh high impedance v ol v oh high impedance high impedance v ol figure 7. 50% 90% 10% 50% 50% 10% 90% 50% 50% t phz t plz t pzh t pzl t pzh t pzl t phz t plz figure 8. figure 9. test circuit figure 10. test circuit
mc54/74hc646 motorola highspeed cmos logic data dl129 e rev 6 312 logic detail 4 20 a0 b0 a1 a2 a3 a4 a5 a6 a7 5 6 7 8 9 10 11 19 b1 18 b2 17 b3 16 b4 15 b5 14 b6 13 b7 d c c q q hc648 hc646 hc646 hc648 v cc v cc hc648 hc646 hc646 hc648 d q q c c a b cab cab sab tab tab tba tba sba cba cba output enable direction 21 3 t ba tba t ab tab sba sab cba cba cab cab 22 2 23 1 btoa source atob source btoa clock atob clock
mc54/74hc646 highspeed cmos logic data dl129 e rev 6 313 motorola outline dimensions j suffix ceramic package case 75802 issue a notes: 1. chamfered contour optional. 2. dimension l to center of leads when formed parallel. 3. dimensioning and tolerancing per ansi y14.5m, 1982. 4. controlling dimension: inch. a b 24 13 12 1 t seating plane 24 pl k e f n c d g m a m 0.25 (0.010) t 24 pl j m b m 0.25 (0.010) t l m note 1 dim min max min max millimeters inches a 1.230 1.265 31.25 32.13 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.020 0.38 0.51 e 0.050 bsc 1.27 bsc f 0.040 0.060 1.02 1.52 g 0.100 bsc 2.54 bsc j 0.007 0.012 0.18 0.30 k 0.110 0.140 2.80 3.55 l 0.300 bsc 7.62 bsc m 0 15 0 15 n 0.020 0.040 0.51 1.01 n suffix plastic package case 72403 issue d c n k f g b 1 24 12 13 l p j seating plane dim a min max min max millimeters 1.240 1.285 31.50 32.64 inches b 0.285 0.305 7.24 7.75 c 0.160 0.200 4.07 5.08 d 0.015 0.021 0.38 0.53 f 0.045 0.062 1.14 1.57 g 0.100 bsc 2.54 bsc j 0.008 0.013 0.20 0.33 k 0.100 0.165 2.54 4.19 l 0.300 0.310 7.62 7.87 n 0.020 0.050 0.51 1.27 p 0.360 0.400 9.14 10.16 notes: 3. dimensioning and tolerancing per ansi y14.5m, 1982. 4. controlling dimension: inch. 5. dimension l to center of leads when formed parallel. 0.25 (0.010) m t a m d 24 pl t a
mc54/74hc646 motorola highspeed cmos logic data dl129 e rev 6 314 outline dimensions dw suffix plastic soic package case 751e04 issue e notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. a b p 12x d 24x 12 13 24 1 m 0.010 (0.25) b m s a m 0.010 (0.25) b s t t g 22x seating plane k c r x 45 m f j dim min max min max inches millimeters a 15.25 15.54 0.601 0.612 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.41 0.90 0.016 0.035 g 1.27 bsc 0.050 bsc j 0.23 0.32 0.009 0.013 k 0.13 0.29 0.005 0.011 m 0 8 0 8 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 how to reach us: usa/europe : motorola literature distribution; japan : nippon motorola ltd.; tatsumispdjldc, toshikatsu otsuki, p.o. box 20912; phoenix, arizona 85036. 18004412447 6f seibubutsuryucenter, 3142 tatsumi kotoku, tokyo 135, japan. 0335218315 mfax : rmf ax0@email.sps.mot.com touchtone (602) 2446609 hong kong : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, internet : http://designnet.com 51 ting kok road, tai po, n.t., hong kong. 85226629298 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. at ypicalo parameters can and do vary in dif ferent applications. all operating parameters, including at ypicalso must be validated for each customer application by customer ' s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur . should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly , any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af firmative action employer . mc54/74hc646/d
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